*/ output reg Alarm, /* This will go high if the alarm time equals the current time, and AL_ON is high. */ input AL_ON, /* If high, the alarm is ON (and Alarm will go high if the alarm time equals the real time). second should be incremented every 10 clock cycles).*/ input LD_alarm, /* If LD_alarm=1, the alarm time should be set to the values on the inputs H_in1, H_in0, M_in1, and M_in0.If LD_alarm=0, the clock should act normally.*/ input STOP_al, /* If the Alarm (output) is high, then STOP_al=1 will bring the output back low. The second time should be set to 0.If LD_time=0, the clock should act normally (i.e. */ input LD_time, /* If LD_time=1, the time should be set to the values on the inputs H_in1, H_in0, M_in1, and M_in0. Valid values are 0 to 5.*/ input M_in0, /*A 4-bit input used to set the least significant minute digit of the clock (if LD_time=1),or the least significant minute digit of the alarm (if LD_alarm=1). Valid values are 0 to 9.*/ input M_in1, /*A 4-bit input used to set the most significant minute digit of the clock (if LD_time=1),or the most significant minute digit of the alarm (if LD_alarm=1). */ input H_in0, /* A 4-bit input used to set the least significant hour digit of the clock (if LD_time=1),or the least significant hour digit of the alarm (if LD_alarm=1). This should be used to generate each real-time second*/ input H_in1, /*A 2-bit input used to set the most significant hour digit of the clock (if LD_time=1),or the most significant hour digit of the alarm (if LD_alarm=1). It should also set the alarm value to 0.00.00, and to set the Alarm (output) low.For normal operation, this input pin should be 0*/ input clk, /* A 10Hz input clock. Input reset, /* Active high reset pulse, to set the time to the input hour and minute (as defined by the H_in1, H_in0, M_in1, and M_in0 inputs) and the second to 00. FPGA projects, VHDL projects, Verilog project module aclock (
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